Period counter vhdl full#
The full VHDL code of the stimuli block can be found below and the output signals can be seen at the Figure 4. The stimuli block generates two signals: Duty cycle as an 8-bits output and a digital enable signal. Figure 3: Simulation block diagramĪn external RTL module was used to generate the stimuli to simulate several cases for the input values and evaluate the response of the PWM module. The desired speed is obtained with the clock wizard block, following the same procedure as in the previous commented FPGA implementation design.
Period counter vhdl generator#
Here, the clock generator source at 200MHz simulates the clock coming from the PS-core.
Thus, a separated simulation test bench-diagram was used, where all the modules can be tested independently. Simulations are performed to test how the modules behave and to debug possible bugs using the internal signal waves. Figure 2: Synthesis and implementation block diagram The simulation Test Bench This core can give a maximum of 250 MHz, therefore the clock output of the processor core is set to 200MHz and the c locking wizard is in charge of getting faster clock speeds. The Zynq-processing system core (PS-core) is used as a clock source and it only provides the clock signal to the FPGA. This diagram is kept as simple as possible, in order to get the greatest performance of the chip. The Vivado tool is based on block diagrams, where the system is prepared to be load into the target board.įor synthesis, implementation and bitstream generation, the design from the block diagram of the Figure 2 was employed.
Table 2: Maximum speed clock frequency of 400 MHz PWM Design diagram This is due all versions of the PWM cannot run at the highest speed and for comparing purposes a lower clock frequency is used. For simplicity, 400 MHz (and 600MHz for speed grade -3) is taken as standard clock speed in all the test in this document if the clock frequency is not detailed. Table 1: Maximum theoretical speed for the Zynq-7000 familyįor the developing a lower clock frequency is employed. Therefore, the next Table 1 shows the maximum theoretical frequency achievable by the PWM module. The bits of resolution is the most limiting factor
Taking this into account, a maximal theoretical speed can be calculated in function of the resolution of the PWM, also the number of bits of the counter. Another devices of this Zynq-7010 family can run faster up to 628 MHz (speed grade -3). This FPGA incorporates the chip Zynq XC7Z010 which could run up to 464MHz (speed grade -1), according to the datasheet of the XC7Z010 device. Several versions are developed with different features and configurable parameters. Therefore, the constraints are studied to know which are the speed limitations.įor this study, the board utilized is the Zybo from Xilinx. Pushing to the Limits of the ZYBO to create the fastest PWM possible in VHDL. The aim of this project is to develop the fastest possible PWM generator IP block using the Zynq FPGA and VHDL programming language. How are the PWM modules tested and compared?.Maximal theoretical speeds by Zynq-7000.
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